Accelerating Functional Verification for Digital Circuit with FPGA Hard Processor System [FPGA硬核处理器系统加速数字电路功能验证的方法]

作者：Liu X.; Yuan G.^*; Qiao S.

来源：JOURNAL OF ELECTRONICS & INFORMATION TECHNOLOGY, 2019, 41(5): 1251-1256.

DOI：10.11999/JEIT180641

• Application Specific Integrated Circuit (ASIC)
• Field-Programmable Gate Array (FPGA) prototype verification
• Functional verification
• SoC FPGA
• System-on-Chip (SoC)

In order to reduce the functional verification cycle of application-specific integrated circuits and on-chip system, a method for accelerating functional verification with FPGA digital hard processor system is proposed. The proposed method combines the advantages of software simulation function verification and field programmable gate array prototype verification, and uses the hard processor system integrated in the on-chip system field programmable gate array device as the verification excitation generation and the function verification coverage analysis unit. It solves the problem that verification speed and flexibility can not be unified. Compared with software simulation verification, the proposed method can effectively shorten the functional verification time of digital circuits; it is superior to existing FPGA prototyping technology in terms of functional verification efficiency and verification of intellectual property reusability.

• 单位
  中国科学院大学