The Design of Clock Synchronization for High Speed Serial Transceivers Inside FPGA [FPGA高速串行收发器时钟同步设计]

作者：Liu Z.; Lei G.; Xu G.-L.

来源：Nuclear Electronics & Detection Technology, 2019, 39(6): 673-677.

• CDR
• Clock synchronization
• Transceiver

When designing timing systems for particle accelerators, FPGA integrated with high-speed serial transceiver is usually used. In order to eliminate the uncertainty of the phase of recovered clock, a method of detecting the clock phase using the recovered data is designed, and then the "reset method" is adopted to achieve the stabilization of the recovered phase. This method does not require additional hardware, only use one serial transceiver and a small number of hardware language programming statements, simple and easy, and has been verified in the laboratory.

• 单位
  中国科学院大学