摘要

A new computational method is proposed to support multiple FFT processing simultaneously.The method can effectively solve the performance loss of memory-based architecture FFT processors due to the computational path pipeline bubbles and the unbalanced throughput of different FFT points.A deeply pipelined WFTA algorithm-based configurable butterfly unit and a new multiple block floating-point processing unit are designed,which can support high precision computing and include one radix-9/two radix-8/three radix-5/four radix-4/five radix-3 in parallel.Based on the proposed method,a multi-mode high performance FFT processor for 4G/5G is implemented,which can support 60 modes including 64~4 096-point FFT/iFFT and 12~3 240-point DFT/iDFT computing.The processor is implemented based on 55 nm CMOS technology,with a 1.46 mm2 layout,supports 1.5GS/s in a single mode and 2.2 GS/s in a mixed mode at 500MHz.It is shown that the proposed processor can support more points and has a better performance than previous designs.

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