摘要

For recording and analyzing the valid output signal of plastic scintillator bar, which placed in the Plastic Scintillator Detector Array(PSD), a Calibration and trigger circuit has been designed. The circuit contains time readout unit and logic trigger unit. The time readout unit is implemented with three channels of analog circuits to acquire the accurate timing result. After this unit, using a FPGA to implement the logic coincidence for the output signal, control the timing process and communicate with the host computer. The host computer can configurate the threshold and determine the channels to coincide. The circuit has been characterized in the lab and proven to satisfy the design requirement. The result shows that it has stable working performance, high counter rate, high uniformity in each channel and easy reconfiguration.