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摘要
The circuit structure optimization method for Basic programmable Logic Element (BLE) of FPGA is studied. Considering finding the solution to the bottleneck problem of low resource utilization efficiency in logic and arithmetic operations with 4-input Look Up Table (LUT), some efforts to improve BLE design based on 4- input LUT are explored. A high area-efficient LUT structure is proposed, and the possible benefits of such a new structure are analyzed theoretically and simulated. Further, a statistical method for evaluation of the post synthesis and mapping netlist is also proposed. Finally, a number of experiments are carried out to assess the proposed structure based on the MCNC and VTR benchmarks. The results show that, compared with Intel Stratix series FPGAs, the optimized structure proposed in this paper improves respectively the area efficiency of the FPGA by 10.428% and 10.433% in average under the MCNC and VTR benchmark circuits.
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