Design of High Speed D/A Converter for Automotive Ethernet PHY [一种用于车载以太网PHY的高速D/A转换器设计]

作者：Zhao Y.^*; Zhu Y.; Tian L.; Wang H.; Feng S.; Li H.

来源：Research & Progress of Solid State Electronics, 2018, 38(6): 439-445.

• CMOS
• Current steering
• Digital-to-analog converter(DAC)
• Physical layer(PHY)
• Spurious free dynamic range (SFDR)

In order to solve the problem that the traditional current source SFDR decreased with the rapid decrease of output impedance at high frequency, the proposed cascode current source was used by passing small current, which improved the dynamic performance of overall DAC. Considering the mutual matching of the current sources in the layout design, a W-type current array layout was taken, which effectively reduced the mismatch caused by gradient error. The proposed DAC employed a full 6-bit thermometer decoder current steering structure with the full swing output current of 40 mA. Based on the SMIC 0.13 um CMOS process, the DAC was 0.35 mm × 0.36 mm in size with 3.3 V power supply for analog circuits and 1.2 V power supply for digital circuits. The test results of tape-out circuit show that the SFDR is 46.60dB at 30 MHz input signal frequency and 1 GHz sampling frequency.

• 单位
  上海交通大学; 中国科学院大学